1. Technical Field
Various embodiments relate to an integrated circuit apparatus, and more particularly, to a semiconductor apparatus.
2. Related Art
In a semiconductor apparatus, signals with various frequencies are used. A signal with a high frequency, such as a clock signal, is generated and divided using a current mode logic (CML) circuit.
A CML circuit is a circuit which outputs a signal swinging with a predetermined frequency between a highest potential level and a lowest potential level in a CML area as a potential level area of a preset range.
A semiconductor apparatus is required to operate with low power consumption, and a clock gating scheme may be taken as one of low power consumption circuit design techniques. The clock gating scheme is a scheme of interrupting a generation of a clock signal according to a mode of a semiconductor apparatus, and is devised to prevent unnecessary power consumption. However, because a circuit unit which continuously uses a clock signal even in a power-down mode exists in a semiconductor apparatus, it is difficult to apply the clock gating scheme in the power-down mode.
FIG. 1 is a configuration diagram of a conventional semiconductor apparatus.
Referring to FIG. 1, a semiconductor apparatus 1 may include a CML circuit unit 11, a first circuit unit 12, a second circuit unit 13, and a control signal generation unit 14.
The CML circuit unit 11 generates differential output signals OUT and OUTB which swing in a CML area, in response to an operation enable signal EN and complementary input signals IN and INB; and provides the differential output signals OUT and OUTB to the first circuit unit 12 and the second circuit unit 13.
The first circuit unit 12 performs an already-designed operation in response to the differential output signals OUT and OUTB of the CML circuit unit 11. In particular, the first circuit unit 12 may be a circuit unit which continuously operates even in a power-down mode and is thus provided with the output signals of the CML circuit unit 11.
The second circuit unit 13 performs an already-designed operation in response to the differential output signals OUT and OUTB of the CML circuit unit 11. The second circuit unit 13 may be a circuit unit of which operation is interrupted in the power-down mode. Accordingly, the second circuit unit 13 does not necessitate the differential output signals OUT and OUTB of the CML circuit unit 11 in the power-down mode.
The control signal generation unit 14 generates a power-down enable signal PD in response to the operation enable signal EN and a power-down mode signal PWDN. The control signal generation unit 14 may be configured, for example, as shown in FIG. 2.
The control signal generation unit 14 shown in FIG. 2 includes an element L11 which generates the power-down enable signal PD of a high level when at least one of the operation enable signal EN and an inverted signal of the power-down mode signal PWDN is enabled, according to a combination of the two signals. Accordingly, the second circuit unit 13 may be interrupted to operate, by the power-down enable signal PD in the power-down mode.
In this manner, although the operation of the second circuit unit 13 may be interrupted in the power-down mode, since the first circuit unit 12 which continuously needs the differential output signals OUT and OUTB of the CML circuit unit 11 exists, the CML circuit unit 11 should also continuously operate in the power-down mode.
The CML circuit unit 11 has advantages in that it has a small swing level, is superior in characteristics with respect to noise and is easy to design.
However, a certain amount of current is consumed regardless of the frequencies of input signals. Accordingly, the same amount of current cannot help but be always consumed even in the power-down mode, as in a normal mode.